SiS M650 Overview
SiS M650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS MuTIOL Technology connecting w/ SiS961 MuTIOL Media IO.
SiS M650 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated `on-die` termination to support Intel Pentium 4 series processors with FSB 100MHz and over clocking up to 133MHz. SiS M650 provides a `12-level` `In-Order`-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4 series based PC systems. It also integrates a high performance 2.7GB/s DDR333 Memory controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition to integrated GUI, SiS M650 also can support external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS M650 and SiS961 MuTIOL Media I/O together. SiS MuTIOL technology is developed into three layers, the `Multi-threaded` I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to `Multi-threaded` I/O Link layer, the `Multi-threaded` I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533 MB/s bandwidth from/to `Multi-threaded` I/O Link layer to/from SiS M650, and the `Multi-threaded` I/O Link Encoder/Decoder in SiS M650 to transfer data w/ 533 MB/s from/to `Multi-threaded` I/O Link layer to/from SiS961.
The memory controller can support both DDR and SDR. It can offer bandwidth up to 2.7GB/s under DDR333, 2GB/s under DDR266 and 1GB/s under PC 133 in order to sustain the bandwidth demand from host processor, as well as the multi I/O masters and AGP masters. Delivering a high performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The SiS M650 adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.
The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture, and a 128 bit 2D accelerator with 1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware acceleration logic to deliver high quality DVD playback. A Dual 12- bit DDR digital video link interfaced to the Video Bridge is incorporated to expand the SiS M650 functionality to support the LCD or TV display. The CRT display and the LCD or TV display can be supported by the Dual View Capability, in the other words that both can generate the display in independent resolutions, color depths, and frame rates. Two separate buses, `Host-t`-GUI in the width of 64 bit, and `GUI-t`-Memory Controller in the width of 128 bit are devised to ensure concurrency of `Host-t`-GUI streaming, and `GUI-t`-MC streaming. In PC133, DDR266 or DDR333 memory subsystem, the 128 bit `GUI-t`-MC bus will attain the AGP4X, AGP 8X equivalent or higher texture transfer rate, respectively. The Memory Controller mainly comprises the Memory Arbiter, the `M-data`/`M-Command` Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP controller, Host Controller, and I/O bus masters based on a default optimized priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the `M-data` queue, any command compliant to the paging mechanism is generated and pushed into the `M-CMD` queue. The `M-data`/`M-CMD` Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by scheduling the command requests in the background when the data requests streamlines in the foreground.
Key features
PC2001 Compliance
High Performance Host Interface
- Support Intel Pentium 4 series CPU with data transfer rate of 533/400 MHz.
- AGTL+ & AGTL compliant bus driver auto compensation
64 Bit High Performance DDR333/DDR266/PC133 Memory Controller
- Supports DDR333/DDR266/200 SDRAM or PC133/100 SDRAM
- Support Up to 2 `un-buffered` DIMM DDR333 or up to 3 `un-buffered` `Double-sided` DIMM DDR266/200
- Up to 1 GB per DIMM with max. memory size up to 3 GB
- Dynamic Clock Enable (CKE) control placing the SDRAM into Suspend to DRAM state
- High performance unified memory controller optimizing the DRAM bus utilization
- Programmable frame buffer size from 8MB and up to 64MB
- Sustains DDR SDRAM CAS Latency at options of 2, 2.5, & 3 clocks
Integrated A.G.P. Compliant Target/66Mhz `Host-to`-PCI Bridge
- AGP v2.0 Compliant
- Supports Additional AGP4X/2X interface and Fast Write Transaction
High Throughput SiS MuTIOL connect to SiS961 MuTIOL Media I/O
- `Bi-directional` 16 bit data bus
- Perform 533MB/s bandwidth in 66MHz x 4 mode
- Distributed arbitration strategy with enhanced mode of contiguous DMA data streaming
- Packet based, pipelining, and split transaction scheme
Dedicated Isochronous Response Queue
- Serves Isochronous downstream transfers responsive to the memory read requests originated from USB or audio/modem controllers
- Offers privilege service to guarantee minimum latency & timely delivery
High Performance & High Quality 3D Accelerator
- `Built-in` a high performance `256-bit` 3D engine
- Supports `Ultra-AGPIITM` up to 2.7GB/s bandwidth
- `Built-in` a high quality 3D engine
High Performance 2D Accelerator
- `Built-in` 128 `double-words` hardware command queue
- `Built-in` Direct Draw Accelerator
- `Built-in` GDI+ Accelerator
- `Built-in` an 1T pipelined `128-bit` BITBLT graphics engine
Complete `TV-OUT`/Digital Flat Panel Solution
`MPEG-2`/1 Video Decoder
- `MPEG-2` ISO/IEC `13818-2` MP@HL and `MPEG-1` ISO/IEC `11172-2` standards compliant
- `Built-in` advanced hardware DVD acceleration logic
- Support AGP bus master/`LFB-mode` code fetching
- Half pixel resolution in motion compensation
- Support VCD, DVD and HDTV (all ATSC modes) decoding
- Direct DVD to TV playback
Video Accelerator
- Supports `YUV-to`-RGB color space conversion
- Supports `bi-linear` video interpolation with integer increments of 1/2048
- Supports graphics and video overlay function
- Supports tearing free double buffer flipping
- Supports RGB555, RGB565, YUV422, and YUV420 video playback format
- Supports filtered horizontal up and down scaling playback
- Supports DVD `sub-picture` playback overlay
- Supports DVD playback `auto-flipping`
- `Built-in` two 120x128 video playback line buffers to support 1920x1080 video playback
- `Built-in` independent Gamma correction RAM
- Supports DCI Drivers
- Supports Direct Draw Drivers
`702-Balls` BGA Package.
1.8V Core with Mixed 1.2V 1.5V 1.8V, 2.5V and 3.3V I/O CMOS Technology
<img src="http://www.sis.com/images/products/diagram/m650.gif" border="0" class="linked-image" />
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